Browsing by Subject Vedic Mathematics
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| Issue Date | Title | Author(s) |
|---|---|---|
| 2013 | FPGA and ASIC Implementation of 16-Bit Vedic Multiplier Using Urdhva Triyakbhyam Sutra. | Jagannatha, K. B.; Lakshmisagar, H. S.; Bhaskar, G. R. |