| 000 | 00524 a2200205 4500 | ||
|---|---|---|---|
| 003 | OSt | ||
| 005 | 20240723161638.0 | ||
| 008 | 240723b |||||||| |||| 00| 0 eng d | ||
| 020 | _a978-81-909-3563-0 | ||
| 040 | _addc | ||
| 041 | _aeng | ||
| 082 |
_223 _a621.391 |
||
| 100 | _aAshenden, Peter J | ||
| 245 |
_aDigital Design _bAn Embedded Systems Approach Using Verilog |
||
| 260 |
_bElesvier, _c2018 _aNew delhi |
||
| 300 | _axx, 557p. | ||
| 650 | _2Digital Design | ||
| 700 | _aAshenden, Peter J | ||
| 942 |
_cR _2ddc |
||
| 999 |
_c399957 _d399957 |
||