Verilog Hdl (Record no. 176719)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00470nam a2200169Ia 4500 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 171227s2017 xx 000 0 und d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 978-81-775-8918-4 |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Palnitkar, Samir |
| 245 ## - TITLE STATEMENT | |
| Title | Verilog Hdl |
| Remainder of title | A Guide to Digital Design and Synthesis |
| 250 ## - EDITION STATEMENT | |
| Edition statement | 2 |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | Chennai |
| Name of publisher, distributor, etc. | Pearson India Education Services Private Limited |
| Date of publication, distribution, etc. | 2017 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | 491 |
| 365 ## - TRADE PRICE | |
| Price amount | 579 |
| 520 ## - SUMMARY, ETC. | |
| Summary, etc. | Verilog,HDL,Verilog HDL |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Verilog HDL |
| 700 ## - ADDED ENTRY--PERSONAL NAME | |
| Personal name | Goel, Prabhu |
| 906 ## - LOCAL DATA ELEMENT F, LDF (RLIN) | |
| a | 26 |
| Withdrawn status | Lost status | Damaged status | Not for loan | Collection code | Home library | Current library | Date acquired | Source of acquisition | Total Checkouts | Total Renewals | Full call number | Barcode | Date last seen | Date last checked out | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| AIT-EC | Acharya Institute of Technology | Acharya Institute of Technology | 22/09/2017 | Sapna Book House | 12 | 15 | 621.392 PAL | 30423 | 06/03/2023 | 03/02/2023 | 12/01/2018 | AIT-Engineering Regular Books |